1. Field of the Invention
This invention relates generally to mini computing systems and more particularly to storge hierarchies having high speed, low capacity storage devices and lower speed high capacity devices coupled in common to a system bus.
2. Description of the Prior Art
The storage hierarchy concept is based on the phenomena that individual stored programs under execution exhibit the behavior that in a given period of time a localized area of memory receives a very high frequency of usage. Thus, a memory organization that provides a relatively small size buffer at the CPU interface, and in addition include various levels of increasing capacity slower storage, can provide an effective access time that lies somewhere in between the range of the fastest and the slowest elements of the hierarchy and provides a large capacity memory system that is "transparent" to the software.
Prior art systems use a large capacity main store or main memory and a small capacity high speed backing store or cache memory associated with the CPU. The cache memory includes a cache directory and a cache data store. The CPU requests a data word from both the main memory and cache. If the data word is in cache then the request of main memory is invalidated. If the data word is not in cache then the requested data word is sent to the CPU and a block of data containing the requested data word is stored in cache. In the prior art the cache is associated with a bus system. Registers in the cache are coupled to the bus system and accept address, data and control signals.
U.S. Pat. No. 3,588,829, issued to Boland and Granito, entitled "Integrated Memory System with Block Transfer to a Buffer Store" described a system whereby a number of stacks are associated with a bus system comprising a buffer storage address bus, a main storage address bus, a storage bus in, a storage bus out and a sink bus.
A transfer address register (TAR) stack is made up of 3 identical registers which receive a fetch request from the buffer storage address bus, tests if the address of the word to be fetched is in any other register in the TAR or a store address register (SAR) stack and sends the address out on the main storage address bus for each word fetched form main memory. The SAR stack receives store request addresses from the CPU over the backing store address bus. Several cycles later the data associated with that address is stored in a storage data buffer (SDB) stack. Data to the SDB comes in on the storage bus in signal lines and out on the storage bus out signal lines. To control the operation is a timing stack which comprises a series of 11 push down registers to synchronize the cycling of main memory with the operation of the system.
The first in - first out priority relationship among the TAR's is indicated by 3 bits stored in each TAR, 1B2 (TAR1 loaded before TAR2), 2B3 and 3B1.
The system comprises 5 busses, 3 for address and 2 for data. The system also comprises 4 stacks, 2 for addresses, 1 for data and 1 for control.